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Part 2 · Physical implementation

Floorplanning, clocks, routing, power, and reliability

Read the floorplan as a resource map, close clock and routing geometry, and choose fixes that survive signal-integrity, IR-drop, electromigration, and antenna analysis.

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9 of 9 practice questions shown.

  1. Q0281Floorplan a four-bank SRAM subsystemPhysical implementation · MediumFloorplan four SRAM banks around traffic, channels, pins, and power.Free
  2. Q0628First response to a macro-channel hotspotPhysical implementation · EasyDiagnose a macro-channel hotspot before applying a local fix.Premium
  3. Q0345Relieve localized routing congestionPhysical implementation · EasyRelieve localized congestion without exporting timing or route risk.Premium
  4. Q0321Trade speed for leakage with multi-Vt cellsPhysical implementation · EasyTrade speed and leakage with multi-Vt cells across critical paths.Premium
  5. Q0525Choose a localized IR-drop repairPhysical implementation · MediumChoose a localized IR-drop repair from current and resistance evidence.Premium
  6. Q0470Minimum parallel straps for IR and EM limitsPhysical implementation · HardSize parallel straps against both IR-drop and EM limits.Premium
  7. Q1051Scale distributed-wire delay with lengthPhysical implementation · EasyRelate distributed wire resistance and capacitance to length.Premium
  8. Q1070Predict opposite-direction crosstalk delayPhysical implementation · EasyPredict delay when a coupled aggressor switches in the opposite direction.Premium
  9. Q0780Explain the routing antenna effectPhysical implementation · EasyExplain process antenna charging and compare repair options.Premium

Physical foundationMake placement and clocking physically possible

A useful floorplan reserves routing, power, and clock resources before placement optimizes local timing. Macro geometry and pin access often dominate the first-order result.

Concept model

Read the floorplan as a resource map

clock sourceroot buffer
branch Abranch B
FF0FF1FF2FF3

Balance insertion delay while controlling skew, slew, power, and routing demand.

Macros
place by trafficKeep strongly connected blocks close while preserving channel width and legal pin access.
Density
local mattersA safe block average does not prevent a hotspot near macro edges or narrow corridors.
Clock
latency + skewCTS trades insertion delay, sink balance, transition, power, and route resources.
Evidence
early routeGlobal routing and trial CTS expose structural problems before detailed implementation.

Macro halos and channels protect routing access, edge pin placement controls long crossings, the power grid consumes tracks, and the clock tree must reach every sink with bounded latency and skew.

Strong answer

A routable floorplan gives high-connectivity regions enough tracks, pin access, vias, and detour options after accounting for macros, halos, blockages, the power grid, and clock resources.

Reason it through

  • Place macros from connectivity and interface direction, then reserve channels based on pin demand and available routing layers.
  • Avoid narrow notches, aligned macro pin walls, and macro corners where local demand can exceed capacity.
  • Validate with early global routing and pin-access analysis because total core utilization cannot reveal local shortages.
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Strong answer

Utilization measures placed-cell area over a region, while congestion compares routing demand with local track and via capacity. Macros, pins, blockages, and directional traffic can exhaust capacity even when cell area is modest.

Reason it through

  • Macro channels and high-pin-density edges can create localized demand that the block average hides.
  • Power straps, clock routes, reserved layers, and routing blockages reduce the capacity available to signal nets.
  • Useful fixes include spreading cells, moving macros or pins, adjusting blockages, improving hierarchy, and changing layer allocation.
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Strong answer

CTS builds a clock network that reaches every sink within transition, capacitance, latency, skew, routing, and power limits across required scenarios. The best tree is the one that supports full-path timing, not necessarily the one with minimum skew.

Reason it through

  • Balancing sink arrival can improve one path group while insertion delay and added buffers increase power and uncertainty elsewhere.
  • Useful skew is intentional only when setup and hold consequences are checked across all interacting paths and corners.
  • Clock gates, generated clocks, nondefault routing, shielding, and local density all affect achievable topology.
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Interconnect integrityClose wires, coupling, and current together

Post-route behavior depends on distributed resistance, capacitance, coupling, and the voltage delivered by the power grid. A timing-only wire fix can move congestion or power risk elsewhere.

Concept model

Two coupled nets share a power delivery problem

aggressorswitches ↑
Ccouplesame direction can speed; opposite direction can slow
victimΔdelay
IR drop
ΔV = I · R
EM
J = I / area
Repair
wider · shorter · more vias/straps
Wire RC
length hurtsResistance and capacitance grow with geometry, so long unbuffered routes can dominate path delay.
Coupling
direction mattersOpposite switching can increase effective load, while same-direction switching can reduce it.
IR drop
V = I · RGrid resistance and simultaneous current lower the voltage available at cell rails.
EM
current densityWire and via geometry must carry required average and peak current within reliability limits.

Long signal routes accumulate RC delay, neighboring transitions change effective coupling, and switching current creates voltage loss in the grid. Signoff uses extracted geometry to analyze all three.

Strong answer

A long route accumulates distributed resistance and capacitance, while coupling capacitance changes the effective load according to relative aggressor and victim switching. Opposite-direction transitions usually slow the victim more than quiet or same-direction neighbors.

Reason it through

  • Buffering divides a long RC line into shorter stages but adds cell delay, power, placement demand, and new timing arcs.
  • Spacing, layer changes, shielding, and slew control reduce coupling when route topology is the root cause.
  • Extraction-aware SI analysis determines whether aggressors overlap in a valid timing window rather than assuming worst-case switching everywhere.
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Strong answer

IR drop limits the voltage lost through resistive paths at required current, while electromigration limits current density in wires and vias. Strap and via sizing must satisfy both constraints in every required activity scenario.

Reason it through

  • A wide strap can reduce resistance, but current still needs enough vias and low-resistance paths through every grid transition.
  • Static analysis emphasizes average demand; dynamic analysis captures localized simultaneous switching and transient droop.
  • Repairs include stronger straps, denser meshes, more vias, closer power sources, cell spreading, decap, and lower local switching demand.
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Strong answer

During fabrication, charge collected on a partially formed conductor can stress a connected gate oxide before a safe discharge path exists. Antenna rules bound exposed conductor area relative to vulnerable gate area for each process stage.

Reason it through

  • A layer jump can break the risky conductor segment by moving part of the route to a layer formed later in the process.
  • An antenna diode provides a discharge path, but it adds junction capacitance, leakage, placement demand, and routing.
  • Repairs must be rechecked against timing, congestion, DRC, and the foundry rule that identified the violation.
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