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Performance · memory · microarchitecture

ASIC Architect Interview Questions

Reason from workload and performance goals into pipelines, memory hierarchy, coherence, interconnect flow control, arbitration, accelerators, and measurable architectural tradeoffs.

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  1. Q068Performance AnalysisSize a FIFO under an unstable sustained rateArch · DVMedium
  2. Q172CoherenceMSI Cache-Coherence Directory ScoreboardDV · ArchHard
  3. Q188Computer ArchitectureControl a link with return creditsArchitecture · InterconnectMedium
  4. Q213Computer ArchitectureSchedule four credited memory clients fairlyArch · MicroarchitectureHard
  5. Q254Performance ControlToken-Bucket Rate-Limit MonitorDV · ArchMedium
  6. Q050RTL DatapathsCompact valid cache-line words in placeStable compaction · Valid bitsMedium
  7. Q057RTL DatapathsDetect duplicate valid cache tagsAssociative compare · Priority encoderMedium
  8. Q243Memory SystemsConstrain eight aligned nonoverlapping memory regionsAddress map · AlignmentHard
  9. Q310Computer ArchitectureRoofline bottleneck for an acceleratorArch · PerformanceMediumP
  10. Q320Computer ArchitectureMatch hit-under-miss responses by transaction IDArch · MicroarchitectureMediumP
  11. Q325Computer ArchitectureRecognize LL/SC reservation failureArch · Atomic operationsEasyP
  12. Q334Computer ArchitectureCache tag, index, and offset bitsComputer Architecture · Architecture / Cache / InterconnectEasyP
  13. Q369Computer ArchitecturePreserve precise state in an out-of-order coreArch · CPUMediumP
  14. Q383Computer ArchitectureSeparate Pipeline Frequency, Throughput, and LatencyArch · PipelineMediumP
  15. Q459Computer ArchitecturePartition a cache addressArch · CacheMediumP
  16. Q468Computer ArchitectureResolve an immediate pipeline data dependencyArch · PipelineEasyP
  17. Q490Computer ArchitectureDeterministic XY mesh routeArchitecture · Network on chipEasyP
  18. Q488Computer ArchitectureReorder an eight-packet sequence windowArch · MicroarchitectureHardP
  19. Q530Computer ArchitectureCheck coherent transactions under reorderingArch · Cache coherenceHardP
  20. Q504Memory SystemsAvoid VIPT cache synonyms with page-offset indexingArch · DesignMediumP
  21. Q573Computer ArchitectureReason for miss-status entriesArchitecture · CacheEasyP
  22. Q590Performance AnalysisPeak and achieved memory bandwidthArch · FWEasyP
  23. Q591CoherenceMESI write miss from InvalidArch · DVEasyP
  24. Q593Computer ArchitectureMaintain true LRU state for four waysArch · DesignMediumP
  25. Q603Computer ArchitectureRemove false dependencies in Tomasulo schedulingArch · Out-of-orderMediumP
  26. Q610Computer ArchitectureTile-level performance modelArch · Performance modelingHardP
  27. Q611Computer ArchitectureTwo-core MESI reference modelArch · MicroarchitectureMediumP
  28. Q717Computer ArchitectureCalculate CPI with branch and cache penaltiesArch · CacheMediumP
  29. Q755Computer ArchitectureSeparate coherence from consistencyArchitecture · Cache coherenceEasyP
  30. Q696Low PowerTurn a Workload into an SoC Architecture BudgetDesign · ArchMediumP

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  • Easy8
  • Medium16
  • Hard6

Related learning

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These are the guides most often linked by questions in this collection.

  1. 01Cache CoherenceReview MSI, MESI, MOESI, ownership, invalidation, intervention, and false sharing.6
  2. 02Cache HierarchyReview mapping, misses, replacement, write policy, VIPT, MSHRs, and nonblocking access.5
  3. 03Out-of-Order ExecutionReview rename, scheduling, physical registers, memory ordering, recovery, and precise retirement.3
  4. 04Budgets and HandoffReview bandwidth, latency, buffering, outstanding work, PPA, and handoff evidence.2
  5. 05Instruction PipelineReview ISA behavior, datapaths, pipeline stages, dependencies, forwarding, stalls, and flushes.2
  6. 06Organization Performance LabsReview CPI, bandwidth, cache and memory timing, AMAT, storage, and EMAT calculations.2
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