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ASIC Architect Interview Questions

Practice the complete ASIC Architect collection

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  1. Q068Performance AnalysisSize a FIFO under an unstable sustained rateArch · DVMedium
  2. Q172CoherenceMSI Cache-Coherence Directory ScoreboardDV · ArchHard
  3. Q188Computer ArchitectureControl a link with return creditsArchitecture · InterconnectMedium
  4. Q213Computer ArchitectureSchedule four credited memory clients fairlyArch · MicroarchitectureHardP
  5. Q254Performance ControlToken-Bucket Rate-Limit MonitorDV · ArchMediumP
  6. Q050RTL DatapathsCompact valid cache-line words in placeStable compaction · Valid bitsMedium
  7. Q057RTL DatapathsDetect duplicate valid cache tagsAssociative compare · Priority encoderMedium
  8. Q243Memory SystemsConstrain eight aligned nonoverlapping memory regionsAddress map · AlignmentHardP
  9. Q310Computer ArchitectureRoofline bottleneck for an acceleratorArch · PerformanceMediumP
  10. Q320Computer ArchitectureMatch hit-under-miss responses by transaction IDArch · MicroarchitectureMediumP
  11. Q325Computer ArchitectureRecognize LL/SC reservation failureArch · Atomic operationsEasyP
  12. Q335Computer ArchitectureCache tag, index, and offset bitsComputer Architecture · Architecture / Cache / InterconnectEasyP
  13. Q372Computer ArchitecturePreserve precise state in an out-of-order coreArch · CPUMediumP
  14. Q387Computer ArchitectureSeparate Pipeline Frequency, Throughput, and LatencyArch · PipelineMediumP
  15. Q466Computer ArchitecturePartition a cache addressArch · CacheMediumP
  16. Q477Computer ArchitectureResolve an immediate pipeline data dependencyArch · PipelineEasyP
  17. Q502Computer ArchitectureDeterministic XY mesh routeArchitecture · Network on chipEasyP
  18. Q500Computer ArchitectureReorder an eight-packet sequence windowArch · MicroarchitectureHardP
  19. Q542Computer ArchitectureCheck coherent transactions under reorderingArch · Cache coherenceHardP
  20. Q516Memory SystemsAvoid VIPT cache synonyms with page-offset indexingArch · DesignMediumP
  21. Q586Computer ArchitectureReason for miss-status entriesArchitecture · CacheEasyP
  22. Q605Performance AnalysisPeak and achieved memory bandwidthArch · FWEasyP
  23. Q607CoherenceMESI write miss from InvalidArch · DVEasyP
  24. Q609Computer ArchitectureMaintain true LRU state for four waysArch · DesignMediumP
  25. Q620Computer ArchitectureRemove false dependencies in Tomasulo schedulingArch · Out-of-orderMediumP
  26. Q627Computer ArchitectureTile-level performance modelArch · Performance modelingHardP
  27. Q628Computer ArchitectureTwo-core MESI reference modelArch · MicroarchitectureMediumP
  28. Q741Computer ArchitectureCalculate CPI with branch and cache penaltiesArch · CacheMediumP
  29. Q781Computer ArchitectureSeparate coherence from consistencyArchitecture · Cache coherenceEasyP
  30. Q720Low PowerTurn a Workload into an SoC Architecture BudgetDesign · ArchMediumP
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ASIC Architect interview preparation

Prepare for ASIC architect interviews with curated questions on pipelines, caches, coherence, memory systems, interconnects, accelerators, and performance.

Reason from workload and performance goals into pipelines, memory hierarchy, coherence, interconnect flow control, arbitration, accelerators, and measurable architectural tradeoffs.