Chapter 8 of 8 · Computer Architecture

Cache coherence

Track readers, writers, dirty ownership, invalidation, intervention, false sharing, and write-policy consequences across private caches.

Move a line between cores Practice questions

Multicore · private caches

A private cache is fast only if every core agrees which copy is valid.

Coherence tracks ownership and visibility for each cache line. Snooping controllers observe transactions, invalidate stale copies, and move the newest data without asking software to repair the view.

Multicore topologyPrivate speed, shared ownership.

Core APrivate L1X · Shared

Core BPrivate L1X · Shared

BusUpgr / ownership request ↓

Coherence pointSnoop fabric or directorySerialize line-X ownership · send invalidations · select responder

↑ data / invalidate / acknowledgement

Shared hierarchyLLC → memory controller → DRAMMay be current or stale depending on write policy and line state

Core A’s write upgrades X from S to M, invalidates Core B’s copy, and makes the private owner responsible for the newest value.

1
Core A reads X and caches a clean copy.
2
Core B reads X and also caches a clean copy.
3
Core A writes X, making its local value newer.
!
Without coherence, Core B could keep and read stale X.

MESI transition explorer

Keep one address coherent across two private caches.

Address X

Model: two private caches, one line, and one backing memory level. Each action completes its transaction before the next begins. Transient states, overlapping requests, invalidation acknowledgements, and evictions are omitted. “Current” describes this backing level, not necessarily DRAM in a multilevel cache hierarchy.

Core A

Core B

Private L1 · Core AINo valid copy

Snoop fabricIdle

Private L1 · Core BINo valid copy

Neither private cache holds X. Memory owns the current copy.

MModified only valid copy, dirty

EExclusive only valid copy, clean

SShared clean copy may exist elsewhere

IInvalid data cannot be used

Protocol invariants

States are an encoding of who may read, who may write, and who owns the newest data.

Single writerAt most one cache may hold write permission.

In MESI, M or E excludes every peer’s valid copy, including Shared copies. A Shared writer must invalidate peers before gaining write permission.

Multiple readersSeveral clean Shared copies may coexist.

Every observer must see a value consistent with the ordered coherence transaction for that line.

Data valueThe newest value lives in memory or one identifiable owner.

MESI M and MOESI M/O mark memory stale; intervention or writeback supplies the current data.

Protocol	States	Key addition	Private clean write	Read of dirty peer	Tradeoff
MSI	M · S · I	Basic invalidation coherence	Needs an ownership transaction because there is no Exclusive state	Modified owner must supply or flush the newest data	Simple, but generates extra traffic for private data
MESI	M · E · S · I	Exclusive marks one clean private copy	Silent E → M transition	Modified owner relinquishes dirty ownership; implementations may forward while updating coherence state	Common balance of private-write efficiency and complexity
MOESI	M · O · E · S · I	Owned permits dirty shared data	Silent E → M transition	Owner can forward dirty data directly while memory remains stale	Less writeback pressure, more controller and verification complexity

MSI

S + local write: request ownership, invalidate sharers, then enter M.

MESI

E + local write: enter M silently. E + remote read: both copies become S.

MOESI

M + remote read: supplier may enter O while the requester enters S and memory remains stale.

Example 64-byte coherence lineCore A counterCore B counterunused bytes

False sharing

Different variables can still fight over one coherence line.

If Core A and Core B repeatedly write separate counters in the same line, ownership ping-pongs on every switch between cores even though the values are logically independent. Repeated writes by the same owner can remain private hits. Coherence works correctly, but transfers and invalidations can reduce throughput because the protocol tracks lines, not language-level variables.

Confirm with invalidation, ownership-transfer, and cache-to-cache traffic counters.
Fix layout with padding, per-core storage, or partitioning, then combine values later.
Do not confuse coherence with consistency: coherence orders one location; consistency constrains ordering across locations.

Write-through

Propagate writes to the next memory level.

Each write is also sent toward the next level, possibly through a write buffer; this does not mean DRAM changes immediately. Peer copies still need invalidation or update. Buffering can hide latency; reducing traffic requires coalescing or another optimization.

Write-back

Keep the newest data in the owning cache.

Writes avoid immediate lower-level traffic, but the protocol must identify the dirty owner and make it supply or write back data when another requester arrives.

Core A has E; Core B now reads the same line. What happens?

Core B issues a read transaction. Core A snoops it and downgrades from Exclusive to Shared because it is no longer the only holder. Core B receives a clean Shared copy, so the final state is S/S. Since the original E line matched memory, no dirty-data recovery is required.

How do write-through and write-back differ under coherence?

Write-through sends each write toward the next memory level, possibly through a buffer, while write-back lets an M or O cache remain the newest owner. Both still need a protocol for other cached copies. Write-through simplifies finding a current lower-level copy at the cost of traffic; write-back reduces traffic at the cost of ownership, intervention, and eviction logic.

Put it into practice

Explain the mechanism. Test your reasoning.

Use the experiment above to support your answer, then apply the idea in the question bank.

Browse architecture questions

You reached the final chapter

Bring the mechanisms together.

Use the question bank to connect pipelines, speculation, memory, and coherence in one explanation.