Multicore · private caches
A private cache is fast only if every core agrees which copy is valid.
Coherence tracks ownership and visibility for each cache line. Snooping controllers observe transactions, invalidate stale copies, and move the newest data without asking software to repair the view.
Core A’s write upgrades X from S to M, invalidates Core B’s copy, and makes the private owner responsible for the newest value.
- 1
Core A reads X and caches a clean copy.
- 2
Core B reads X and also caches a clean copy.
- 3
Core A writes X, making its local value newer.
- !
Without coherence, Core B could keep and read stale X.
MESI transition explorer
Keep one address coherent across two private caches.
Neither private cache holds X. Memory owns the current copy.
Protocol invariants
States are an encoding of who may read, who may write, and who owns the newest data.
M or E excludes every peer’s valid writable copy. A Shared writer must invalidate peers first.
Every observer must see a value consistent with the ordered coherence transaction for that line.
MESI M and MOESI M/O mark memory stale; intervention or writeback supplies the current data.
| Protocol | States | Key addition | Private clean write | Read of dirty peer | Tradeoff |
|---|---|---|---|---|---|
| MSI | M · S · I | Basic invalidation coherence | Needs an ownership transaction because there is no Exclusive state | Modified owner must supply or flush the newest data | Simple, but generates extra traffic for private data |
| MESI | M · E · S · I | Exclusive marks one clean private copy | Silent E → M transition | Modified owner relinquishes dirty ownership; implementations may forward while updating coherence state | Common balance of private-write efficiency and complexity |
| MOESI | M · O · E · S · I | Owned permits dirty shared data | Silent E → M transition | Owner can forward dirty data directly while memory remains stale | Less writeback pressure, more controller and verification complexity |
S + local write: request ownership, invalidate sharers, then enter M.
E + local write: enter M silently. E + remote read: both copies become S.
M + remote read: supplier may enter O while the requester enters S and memory remains stale.
Update lower memory on every write.
Memory stays current, but peer caches can still contain stale copies. The coherence protocol must invalidate or update them. Traffic is high unless a write buffer absorbs latency.
Keep the newest data in the owning cache.
Writes avoid immediate lower-level traffic, but the protocol must identify the dirty owner and make it supply or write back data when another requester arrives.
Core A has E; Core B now reads the same line. What happens?
Core B issues a read transaction. Core A snoops it and downgrades from Exclusive to Shared because it is no longer the only holder. Core B receives a clean Shared copy, so the final state is S/S. Since the original E line matched memory, no dirty-data recovery is required.
How do write-through and write-back differ under coherence?
Write-through immediately updates the next memory level, while write-back lets an M or O cache remain the newest owner. Both still need a protocol for other cached copies. Write-through simplifies finding a current lower-level copy at the cost of traffic; write-back reduces traffic at the cost of ownership, intervention, and eviction logic.