| 1 · Specification | Decompose interfaces, features, and behaviors. Rank ordering, concurrency, CDC, power, precision, and forward progress by risk. | Define ordering domains, legal routing, QoS and fairness, deadlock and livelock, and credit or backpressure loops. | Define temporal correctness, bank conflicts, refresh starvation, RAW hazards, address aliasing, and cache coherency races when applicable. | Define DMA-to-compute synchronization, buffer lifecycle, unaligned accesses, quantization and precision, and circular waits among engines. |
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| 2 · Golden model | Choose the source of truth at the lowest abstraction that can independently answer the required question. | Use a routing predictor plus a global in-flight tracker keyed by transaction ID. Predict legal destination, not one fixed adaptive route. | Use a sparse memory model with per-bank state. For cache, add a global directory or coherence-state model. | Use a bit-accurate DPI-C, C++, or Python numerical oracle at the architectural commit point plus a descriptor-lifecycle ownership model. |
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| 3 · Testbench architecture | Use reusable agents per interface, a virtual sequencer for cross-interface scenarios, a latency-tolerant scoreboard, and an SVA layer. | Use ingress agents, egress monitors, distributed scoreboard partitions, and one global tracker for out-of-order matching. | Use AXI or CHI front-end agents, a DFI or DRAM model, a two-stage scoreboard for write buffers versus memory, and per-bank trackers. | Use command and AXI-Stream agents, a symbiotic SRAM ownership monitor, and a result collector at the write-back boundary. |
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| 4 · Active path | Progress from directed bring-up to constrained random, stress, then disruption such as reset, power, or backpressure during traffic. | Create many-to-one congestion, mixed IDs, QoS starvation, adaptive routing, and in-flight reset, link retrain, or reconfiguration. | Shape row hit and miss traffic, bank thrash, refresh overlap, same-address RAW sequences, and power-down or self-refresh exit. | Maximize outstanding descriptors, use unaligned bursts, stall outputs mid-compute, and exercise NaN, maximum, minimum, and tail tiles. |
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| 5 · Passive path | Use SVA for protocol, scoreboards for data, and watchdog or age tracking for liveness. | Check per-ID ordering, credit conservation, drops and duplicates, and dependency-aware forward progress. | Check command legality at issue, refresh windows, ECC or parity injection, and coherence transitions. | Compare bit-accurate results at architectural write-back, check buffer reuse, and assert saturation and rounding rules. |
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| 6 · Coverage | Map feature, cross, register, temporal state, and performance coverage directly to the testplan. | Cross source, destination, ID, burst, congestion, outstanding depth, and QoS aging or fairness. | Cross bank, row hit or miss, timing corner, refresh overlap, ECC type, and cache state versus request type. | Cross tile size, stride, quantization mode, buffer occupancy, compute utilization, and descriptor-queue depth. |
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| 7 · Performance | Track latency distributions, throughput, utilization, starvation, and deadlock evidence. | Measure tail latency by class, bandwidth per master, and starvation under sustained high-priority load. | Measure page-hit rate, bank parallelism, sustained bandwidth, and prove refresh or write-drain cannot block a request forever. | Compare predicted and observed tile latency, enforce utilization floors, and prove no circular wait among DMA, compute, and output. |
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| 8 · Sign-off | Reach stable directed and constrained-random regressions, close meaningful coverage, and demonstrate convergence. | Drain every in-flight transaction at end of test, prove long-run fairness, and show no progress violation under stress. | Close timing corners and long-run refresh stability, then sign off ECC, scrub, and power-state recovery flows. | Meet the performance envelope under stress, preserve numerical stability, and show no buffer leak or descriptor stall. |
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