System verification strategy

Build the verification plan and oracle

Adapt a reusable strategy matrix to fabrics, memories, and accelerators, then study complete worked system-design answers.

Keep the source of truth, observation path, stress model, and exit evidence explicit so every verification decision can be reviewed.

Strategy explorer

One planning spine. Three different systems.

Inspect each decision in the generic plan, then compare the concrete obligation for the selected subsystem.

SELECT & INSPECT

FabricSELECT A RESPONSIBILITY

Scroll horizontally to inspect all responsibilities →

Planning decision

1 · Specification

Define ordering domains, legal routing, QoS and fairness, deadlock and livelock, and credit or backpressure loops.

Inspect the context

The generic decision

Decompose interfaces, features, and behaviors. Rank ordering, concurrency, CDC, power, precision, and forward progress by risk.

Inspect checks & coverage

Plan review

Make the answer reviewable.

For this decision, record the assumption, the owner, the failure it prevents, and the evidence that would change your conclusion.

Keep the same eight decisions, but make every answer specific to the design.

Select, inspect, compare.

Fabric. 1 · Specification.

Open the eight-decision matrix

Reusable answer spine

Eight decisions, adapted to the design.

The generic column is the invariant interview structure. The other columns show how the answer changes for a transactional fabric, memory/cache subsystem, or DMA/accelerator.

Eight verification-strategy decisions compared across generic, fabric, memory, and accelerator designs.
Step	Generic	Fabric / NoC	Memory / Cache	DMA / Accelerator
1 · Specification	Decompose interfaces, features, and behaviors. Rank ordering, concurrency, CDC, power, precision, and forward progress by risk.	Define ordering domains, legal routing, QoS and fairness, deadlock and livelock, and credit or backpressure loops.	Define temporal correctness, bank conflicts, refresh starvation, RAW hazards, address aliasing, and cache coherency races when applicable.	Define DMA-to-compute synchronization, buffer lifecycle, unaligned accesses, quantization and precision, and circular waits among engines.
2 · Golden model	Choose the source of truth at the lowest abstraction that can independently answer the required question.	Use a routing predictor plus a global in-flight tracker keyed by transaction ID. Predict legal destination, not one fixed adaptive route.	Use a sparse memory model with per-bank state. For cache, add a global directory or coherence-state model.	Use a bit-accurate DPI-C, C++, or Python numerical oracle at the architectural commit point plus a descriptor-lifecycle ownership model.
3 · Testbench architecture	Use reusable agents per interface, a virtual sequencer for cross-interface scenarios, a latency-tolerant scoreboard, and an SVA layer.	Use ingress agents, egress monitors, distributed scoreboard partitions, and one global tracker for out-of-order matching.	Use AXI or CHI front-end agents, a DFI or DRAM model, a two-stage scoreboard for write buffers versus memory, and per-bank trackers.	Use command and AXI-Stream agents, a symbiotic SRAM ownership monitor, and a result collector at the write-back boundary.
4 · Active path	Progress from directed bring-up to constrained random, stress, then disruption such as reset, power, or backpressure during traffic.	Create many-to-one congestion, mixed IDs, QoS starvation, adaptive routing, and in-flight reset, link retrain, or reconfiguration.	Shape row hit and miss traffic, bank thrash, refresh overlap, same-address RAW sequences, and power-down or self-refresh exit.	Maximize outstanding descriptors, use unaligned bursts, stall outputs mid-compute, and exercise NaN, maximum, minimum, and tail tiles.
5 · Passive path	Use SVA for protocol, scoreboards for data, and watchdog or age tracking for liveness.	Check per-ID ordering, credit conservation, drops and duplicates, and dependency-aware forward progress.	Check command legality at issue, refresh windows, ECC or parity injection, and coherence transitions.	Compare bit-accurate results at architectural write-back, check buffer reuse, and assert saturation and rounding rules.
6 · Coverage	Map feature, cross, register, temporal state, and performance coverage directly to the testplan.	Cross source, destination, ID, burst, congestion, outstanding depth, and QoS aging or fairness.	Cross bank, row hit or miss, timing corner, refresh overlap, ECC type, and cache state versus request type.	Cross tile size, stride, quantization mode, buffer occupancy, compute utilization, and descriptor-queue depth.
7 · Performance	Track latency distributions, throughput, utilization, starvation, and deadlock evidence.	Measure tail latency by class, bandwidth per master, and starvation under sustained high-priority load.	Measure page-hit rate, bank parallelism, sustained bandwidth, and prove refresh or write-drain cannot block a request forever.	Compare predicted and observed tile latency, enforce utilization floors, and prove no circular wait among DMA, compute, and output.
8 · Sign-off	Reach stable directed and constrained-random regressions, close meaningful coverage, and demonstrate convergence.	Drain every in-flight transaction at end of test, prove long-run fairness, and show no progress violation under stress.	Close timing corners and long-run refresh stability, then sign off ECC, scrub, and power-state recovery flows.	Meet the performance envelope under stress, preserve numerical stability, and show no buffer leak or descriptor stall.

Explore three worked systems

Worked system-design answers

Three prompts, answered end to end.

Each answer follows spec clarification, source of truth, architecture, stimulus, passive checks, coverage, performance, and sign-off.

Worked system design · complete answer path

Multi-bank DMA + Shared Memory + Interrupts

01 · Clarify the specification

Clarify descriptor fetch, channels and banks, per-channel ordering, maximum outstanding work, and the exact completion point. Ask about burst size, alignment, error handling, reset, and power-gating behavior.

02 · Golden model

Request a model that consumes descriptors and memory contents and predicts reads, writes, final memory state, and completion events. A focused Python model is sufficient when its contract is explicit.

03 · Testbench architecture

At block level, instantiate DMA agents, memory or AXI agents, and interrupt or status agents. Reuse them at top level and scale N banks through one configuration object controlling topology, arbitration, and outstanding depth.

04 · Stimulus

Bring up one channel and one descriptor with known data. Randomize size, alignment, stride, bursts, address ranges, and simultaneous banks. Add heavy backpressure, ready/valid timing variation, mid-transfer reset, power gating, invalid descriptors, and out-of-range addresses.

05 · Scoreboard and checkers

Bind protocol SVA for handshake stability, burst legality, and response rules. Use a memory-model scoreboard for reads, writes, and final content. Match out-of-order completion by tag or descriptor ID, or use per-channel queues when the contract is ordered. Age work per bank to detect liveness failures.

06 · Coverage

Separate interface coverage, register-field and configuration coverage, topology crosses across bank, channel, arbitration, and outstanding depth, plus reset-during-transfer, completion ordering, and error or retry temporal coverage.

07 · Performance

Measure bytes per cycle, completion-latency distributions, bank fairness, outstanding-depth efficiency, and QoS under contention. Preserve them as regression metrics so performance regressions fail visibly.

08 · Regression and sign-off

Require testplan and functional-coverage closure, stable non-flaky regressions, low triage load, converging bugs, and a targeted regression for every high-severity bug class.

Worked system design · complete answer path

Coherent Interconnect / NoC Fabric

01 · Clarify the specification

Pin down ordering by ID and address, legal reorderings, error reporting, routing and virtual channels, coherency, snoops, and atomic operations.

02 · Golden model

Use a reference that predicts legal response orderings and final memory state. If full coherency is too heavy, combine a legal-transaction checker with a focused consistency model for the critical flows.

03 · Testbench architecture

Build reusable master and slave or memory agents. Drive port count, address maps, and route rules from topology configuration. Keep local protocol monitors at ports and a centralized model for global invariants.

04 · Stimulus

Start at one master and one slave, then scale to mixed reads, writes, atomics, IDs, bursts, and backpressure. Add congestion, link flaps, resets, clock gating, and error injection.

05 · Scoreboard and checkers

Assert stability, credits, virtual-channel rules, and legal transitions. Match requests and responses by ID, tag, address, or transaction handle in associative structures, and age missing responses.

06 · Coverage

Cross masters, slaves, virtual channels, IDs, bursts, and backpressure. Cover routes, congestion points, arbitration outcomes, retries, timeouts, and reset recovery.

07 · Performance

Measure latency under contention, throughput per master, fairness, and head-of-line blocking, then trend the results across regressions.

08 · Sign-off

Require functional closure and long random stability. Convert long-tail escapes and clustered bugs into instrumented, scenario-based directed regressions.

Worked system design · complete answer path

Interrupt Controller / Event Router

01 · Clarify the specification

Clarify sources, priorities, masks, edge versus level semantics, aggregation, and reset or low-power behavior.

02 · Golden model

Use a behavioral predictor that consumes input events and register state and produces expected IRQ lines and status bits, including priority and mask interactions.

03 · Testbench architecture

Combine a RAL programming agent, an event-injection agent, and an IRQ observation agent. Make source and line counts configurable.

04 · Stimulus

Direct single-source trigger, mask and unmask, priority updates, clear behavior, and edge or level cases. Randomize event bursts and masks under load, then collide storms with reset, clock gating, and power transitions.

05 · Scoreboard and checkers

Assert IRQ stability, clear semantics, and no lost level interrupt. Predict IRQ assertion, deassertion, and status. Age injected events until they are visible or serviced.

06 · Coverage

Cross priority, mask state, edge or level type, clear path, aggregation mode, and power or reset sequence.

07 · Performance

Measure event-to-IRQ latency and prove that interrupt storms do not starve eligible lower-priority work beyond the architectural bound.

08 · Sign-off

Close coverage, sustain long interrupt storms with power transitions, and require stable bug convergence.