Failure modes to reusable verification patterns
Verification Case Studies
Learn how experienced verification engineers reshape stimulus, scoreboards, models, assertions, and infrastructure when the design resets, reorders, starves, corrupts, interrupts, or scales.
The cases are grouped by the engineering contract they share, so you can transfer one solution pattern across many protocols and subsystems.The case library
Start with a failure.
Pick a mechanism. Open an experiment.
13 case studies
Mid-test reset+Does old work survive reset?
Mid-Test Reset Orchestration
A driver completes a stale handshake or leaves valid asserted across reset.
Enter the lab ↗Power gating+Release isolation too early.
Power Gating, Isolation, and Retention
An output is not clamped while its source island is off.
Enter the lab ↗Clock gating+Which edge accepts the transfer?
Clock Gating and Wake-Up Integrity
The gated clock continues toggling after the IP satisfies its idle threshold.
Enter the lab ↗Ordering+A legal interleave or a violation?
Out-of-Order Ordering and Memory Consistency
A same-ID response returns in the wrong order.
Enter the lab ↗QoS & fairness+Can a busy requester starve?
QoS, Fairness, and Backpressure
A low-priority request waits beyond its allowed starvation bound.
Enter the lab ↗Negative testing+Reject the packet. Reuse its ID.
Negative Testing and Exception Scoreboarding
An expected CRC or ECC rejection appears as a false data mismatch.
Enter the lab ↗Interrupts+The tenth event—or the timeout?
IRQ Subsystem Verification
An event is dropped and the expected IRQ never arrives.
Enter the lab ↗Deadlock & livelock+No progress. What does that prove?
Deadlock, Livelock & Credit Watchdogs
Items remain in flight while the completion counter does not change for the watchdog window.
Enter the lab ↗Configurable testbenches+Can an override change an instance?
Dynamic Reconfiguration & Polymorphic Testbenches
An override is installed after creation and has no effect.
Enter the lab ↗Broadcast+Count recipients, not responses.
Broadcast Control Plane & Global TB Messaging
One or more agents miss the global event and retain stale state.
Enter the lab ↗Performance+What did the sample miss?
Performance Verification Framework
The design passes functionally but misses sustained bandwidth or latency targets.
Enter the lab ↗Clock crossings+Move the clocks. Hold the data.
CDC & RDC Dynamic Verification
Request changes again before acknowledgement and the destination loses or duplicates an event.
Enter the lab ↗Firmware ↔ hardware+What arrives at the timeout?
Firmware & Hardware-Software Interface Verification
A firmware-equivalent sequence no longer matches the current software driver or header definitions.
Enter the lab ↗Independent observation
Look past the passing test.
A useful verification result connects the observed behavior to a requirement, a trustworthy model, and a checker that could expose the failure.
From cases to complete systems
Design the verification strategy.
Apply the same reasoning to AXI fabrics, memory controllers, accelerators, coherency, and control subsystems from planning through sign-off.
- System designVerification StrategyPlan the source of truth, testbench, active and passive paths, coverage, performance evidence, regressions, and exit criteria.Open the strategy guide
- Learning pathASIC Design VerificationConnect UVM, SystemVerilog Assertions (SVA), coverage, debug, and reusable verification architecture.Open verification path