System verification strategy
Shape the UVM architecture around the risk
Part 3 · Reference architectures
Compare five native block diagrams for fabrics, memory systems, accelerators, coherency, and control-heavy subsystems.
Keep the source of truth, observation path, stress model, and exit evidence explicit so every verification decision can be reviewed.
Native UVM block diagrams
Five reference architectures.
Expand each design to see its stimulus plane, DUT boundary, passive observation, source of truth, coverage, disruption scenarios, and the mechanism that makes the environment specific to the risk.01 · UVM reference architecture
Transactional Fabric DV
Verify routing, ordering, data integrity, flow control, global visibility, fairness, and forward progress when packets can enter and leave through many ports.
01 · UVM reference architecture
Transactional Fabric DV
Verify routing, ordering, data integrity, flow control, global visibility, fairness, and forward progress when packets can enter and leave through many ports.
Coordinates ingress, egress, congestion, reset, reconfiguration, and recovery.
AXI or CHI ingress acceptance creates the global in-flight entry; agents also model backpressure and credit return.
NoC mesh or crossbar; perform block-level testing per mesh and recovery checks during reset or reconfiguration.
AXI, CHI, or memory models provide requests, responses, packets, and snoops on every egress.
Detects deadline, livelock, starvation, or dependency-local loss of progress.
Hash map for lifecycle, destination, routed information, and drop or duplicate detection.
One partition per destination, keyed by destination, ID, and flow rather than one FIFO.
Predicts legal destinations and reference memory behavior.
Destination, ID, flow, route, congestion, ordering, disruption, and recovery crosses.
- 01Coordinate the scenario
- 02Drive the DUT boundary
- 03Observe independently
- 04Predict and compare
- 05Close the risk
- Legal destination for fixed or adaptive routing
- Order within every required ID or flow domain
- No corruption, duplication, or drop
- Ready/valid or credit accounting without overflow or underflow
- Deadlock, livelock, starvation, and QoS
- Many-to-one congestion with mixed IDs and flow classes
- Adaptive-route alternatives and blocked outputs
- Reset, link retrain, or reconfiguration with traffic in flight
- Credit pressure, retries, duplicates, drops, and late responses
- Source × destination × ID × burst
- Legal route × congestion point
- Outstanding depth × buffer
- QoS age × arbitration outcome
- Latency distribution and tail by class
- Throughput and bandwidth per master
- Fairness and starvation bounds
- End-of-test in-flight drain
02 · UVM reference architecture
Memory Subsystem DV
Prove data correctness only when command ordering, bank state, global timing windows, refresh, ECC, aliasing, and liveness all remain legal.
02 · UVM reference architecture
Memory Subsystem DV
Prove data correctness only when command ordering, bank state, global timing windows, refresh, ECC, aliasing, and liveness all remain legal.
Coordinates row locality, refresh overlap, errors, power modes, and frequency changes.
AXI, CHI, or DFI driver, sequencer, monitor, and TLM path; applies command, data, and backpressure.
Reactive slave, sparse memory, backdoor interface, and ECC logic across DFI or DRAM command/data.
DRAM controller under block-level testing per bank.
- 01Queuebank · row · age
- 02Check legalitybank state + global timing
- 03Select + issueACT · RD · WR · PRE · REF
- 04Updatestate · credits · completion
Bank FSM with timing SVA for idle, activating, active, precharging, and refreshing.
Sliding-window buffer and constraint checks for tFAW, tRRD, and other cross-bank rules.
Error generator, injection tracking, detection, correction, and reporting.
Latency histogram, bandwidth, page-hit calculation, watchdog, age queue, and starvation detection.
Sparse associative model or TLM FIFO plus an address-map and alias-conflict checker with backdoor comparison.
Bank, row locality, timing corner, refresh overlap, ECC type, and sampling crosses.
- 01Coordinate the scenario
- 02Drive the DUT boundary
- 03Observe independently
- 04Predict and compare
- 05Close the risk
- Per-bank and bank-group protocol timing
- Command legality for current bank state
- Read/write integrity and ECC or parity behavior
- Every row refreshed within its required window
- Bank interleaving, page-hit rate, and turnaround efficiency
- Address aliasing, row conflict, and worst-case activate/precharge thrash
- Page hits, misses, bank thrash, and address aliases
- Refresh under heavy read/write traffic
- Write-drain and read/write turnaround pressure
- Power-down, self-refresh, DFI frequency change, and retraining
- ECC injection without consuming front-door bandwidth
- Bank × row hit/miss × command sequence
- Refresh overlap × read/write traffic
- Maximum activate-window stress
- ECC type × correction path
- Latency distribution and sustained bandwidth
- Bank parallelism utilization
- Page-hit rate and turnaround efficiency
- No starvation from refresh or write drain
03 · UVM reference architecture
Data Engine / Accelerator DV
Coordinate DMA, local buffers, compute, and write-back while remaining bit-accurate across tiling, strides, unaligned data, quantization, and millions of operations.
03 · UVM reference architecture
Data Engine / Accelerator DV
Coordinate DMA, local buffers, compute, and write-back while remaining bit-accurate across tiling, strides, unaligned data, quantization, and millions of operations.
Coordinates command, data/weight streams, result collection, and buffer ownership.
Programs configuration and dispatches tasks and command addresses.
Drives data and weights with tiling, stride, unaligned bursts, Data/Last, and backpressure.
Reactive sink that controls Ready and collects committed result data.
DMA plus systolic array, tested block by block at each pipeline stage.
- DMA
- Local buffer
- Compute array
- Write-back
Tracks bank lock and release, ping-pong races, double allocation, and premature reuse.
P99 latency, bubble detection, tile lifetime, and compute-idle threshold under sufficient bandwidth.
Checks INT8/FP16 saturation, RNE/RTZ rounding, Inf/NaN, and accumulation rules.
Bit-accurate C++ or Python/NumPy matrix calculation at architectural write-back.
Tile and stride configurations, quantization modes, buffer states, and handoff corners.
- 01Coordinate the scenario
- 02Drive the DUT boundary
- 03Observe independently
- 04Predict and compare
- 05Close the risk
- INT8 or FP16 saturation, rounding, overflow, NaN, and Inf rules
- 2D or 3D tiling, strides, tails, padding, and masks
- DMA/compute handoff and output backpressure
- Unaligned byte shifting and cross-lane steering
- Results visible only at the architectural commit boundary
- Ping-pong buffer races and premature bank reuse
- Unaligned 128-bit transfer beginning at an offset such as 0x3
- DMA stall with compute active and output backpressure
- Tail tiles, masks, extreme numeric values, and mode changes
- Tile size × stride × quantization mode
- Buffer occupancy × ownership transition
- Descriptor depth × output backpressure
- Rounding × saturation × numeric corner
- Tile latency versus predicted envelope
- MAC and array utilization floor
- Sustained throughput and bubble rate
- No descriptor or resource circular wait
04 · UVM reference architecture
Coherency Model DV
Prove one shared-memory truth across concurrent out-of-order caches and ensure no latency or race produces divergent values or silent data corruption.
04 · UVM reference architecture
Coherency Model DV
Prove one shared-memory truth across concurrent out-of-order caches and ensure no latency or race produces divergent values or silent data corruption.
Virtual sequence coordinates conflicting requests with precise cycle offsets.
CPU or GPU drivers, monitors, and local cache models issue requests, snoops, data, and backpressure.
Home node arbitrates ownership, snoops, memory requests, and data.
Consumes memory requests and returns memory data behind the home node.
Uses the directory model to predict the correct snoop response and compare it with RTL.
Checks the implementation's legal stable and transient state transitions plus atomic or exclusive operations.
Tracks write/write and read/write races plus snoop-broadcast behavior.
Central architectural truth for payload, stable ownership, sharers, and allowed serialization outcomes without over-constraining legal transient encodings.
Periodic or end-of-test dumps compare local caches and main memory with the directory to detect SDC.
MESI transitions, race scenarios, false sharing, and cache thrashing.
- 01Coordinate the scenario
- 02Drive the DUT boundary
- 03Observe independently
- 04Predict and compare
- 05Close the risk
- Legal MESI or MOESI transitions
- No write to Shared without ownership and invalidation
- Write/write and read/write races
- Snoop and broadcast delivery and response aggregation
- Atomic LL/SC or read-modify-write behavior
- Same-line write/write ownership collision
- Read racing a write before global visibility
- False sharing and cache thrashing
- Snoop saturation, atomics, and exclusive failure
- Prior state × request × response × next state
- Race type × relative cycle offset
- Snoop fanout × aggregation result
- Atomic type × intervening request
- Snoop bandwidth and response latency
- Ownership-transfer latency
- Directory and home-node contention
- Zero silent-data-corruption mismatches
05 · UVM reference architecture
Control Flow DV
Prove legal state transitions, asynchronous event handling, reset and power-state correctness, deterministic recovery, and forward progress for software-visible control state.
05 · UVM reference architecture
Control Flow DV
Prove legal state transitions, asynchronous event handling, reset and power-state correctness, deterministic recovery, and forward progress for software-visible control state.
Power-aware bring-up, clock switch, power collapse, and reset-during-traffic coordination.
APB or AHB programming, illegal-sequence injection, and software-visible state access.
Injects asynchronous interrupts, power requests, and reset collisions.
Permanent stalls, late acknowledgements, timeout testing, and acknowledgements during reset or power transition.
Power, interrupt, reset, or clock controller.
- IDLE
- QUIESCE
- TRANSITION
- RESTORE
Legality, dead-end detection, and State × Event arc coverage.
Crossings, glitches, warm/cold reset, retention, and domain-release sequencing.
State age, progress timeout, starvation, and dependency-loop detection.
Isolation, retention restore, and X-propagation into active domains.
Next-state and output prediction for legal scenarios and recovery.
Sticky versus non-sticky state and allowed changes for each power or reset condition.
FSM arcs, power/reset scenarios, and error-recovery paths.
- 01Coordinate the scenario
- 02Drive the DUT boundary
- 03Observe independently
- 04Predict and compare
- 05Close the risk
- Every legal FSM arc and no dead-end state
- Exit from error states and eventual return to IDLE or RUN
- Interrupt, power, and reset collisions around handshakes
- CDC/RDC synchronization and reset release by domain
- Illegal software programming during transition
- Timeouts produce architectural error instead of silent hang
- Retention, quiesce, isolation, restore, and reinitialization
- Interrupt, reset, and power request on the same cycle
- Late or permanently missing acknowledgement
- Software writes during a clock or power transition
- Warm reset with retained and non-retained state
- Power collapse before quiesce and recovery after restore
- State × event × exit path
- Error state × recovery mechanism
- Power state × reset type × sticky state
- Handshake age × injected response behavior
- Event-to-response and recovery latency
- Bounded state age
- No dependency-loop or starvation timeout
- Correct quiesce and wake latency