1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ778

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Q778DesignNVIDIAASIC interview problem

Quarantine traffic after peer reset

TechniquesDesignCDCResetQuarantineTraffic

DifficultyMedium

TopicCDC and Reset

LanguageSystemVerilog

Requirements4 checkpoints

Problem

A local interface sees an already synchronized peer_reset_ok signal. It must wait for two consecutive high samples before accepting traffic after any peer reset. Implement the local reset-quarantine logic in SystemVerilog.

Starting declarationSystemVerilog

input logic clk, rst_n, peer_reset_ok;
input logic in_valid;
output logic in_ready, quarantined;

Example input and output

Use this case to check your interpretation

Input

After local reset, sample peer_reset_ok high on two consecutive rising edges.

Output

in_ready remains 0 after the first high sample and becomes 1 after the second.

Explanation

The quarantine releases only when the two-sample recovery counter observes uninterrupted peer readiness.

Requirements (4)

When rst_n=0 at an edge, set quarantined=1, clear the high-sample count, and drive in_ready=0.
While peer_reset_ok=0, remain quarantined and clear the high-sample count.
Leave quarantine only after peer_reset_ok has been high on two consecutive rising edges.
Set in_ready=!quarantined. During a stall (in_valid && !in_ready), accept nothing; in_valid cannot change quarantine state.