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DescriptionQ093
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Q093ArchIntelASIC interview problem

Cache tag, index, and offset bits

TechniquesComputer ArchitectureArchitecture / Cache / Interconnectcache tag, index, and offset bits
DifficultyEasy
TopicComputer Architecture
LanguageSystemVerilog
Format4 choices
01

Problem

A physically addressed 1 MiB cache is 8-way set associative, has 64-byte lines, and uses 48-bit physical addresses. How many offset, set-index, and tag bits are required?

02

Answer choices (4)