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Hardware interview practice

Cache tag, index, and offset bits

EasyComputer ArchitectureSystemVerilog

A physically addressed 1 MiB cache is 8-way set associative, has 64-byte lines, and uses 48-bit physical addresses. How many offset, set-index, and tag bits are required?

Choose one

Answer choices

  1. A. 6 offset bits, 14 set-index bits, and 28 tag bits.
  2. B. 8 offset bits, 11 set-index bits, and 29 tag bits.
  3. C. 6 offset bits, 10 set-index bits, and 32 tag bits.
  4. D. 6 offset bits, 11 set-index bits, and 31 tag bits.
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