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Hardware interview practice

UVM monitor for a framed byte stream

MediumSystemVerilog & UVMSystemVerilog

A byte interface marks the first and last byte of each accepted packet. Write the core SystemVerilog/UVM monitor code that publishes complete packets.

Starting point

Question code

input logic clk, rst_n;
input logic valid, ready, sop, eop;
input logic [7:0] data;
uvm_analysis_port #(packet_item) ap;
Reviewed example

Work through one case

Input
Accepted beats are 8'h11 with sop=1, then 8'h22, then 8'h33 with eop=1.
Expected output
Publish exactly one packet_item containing bytes {11,22,33}.

The SOP beat creates the item, each valid-ready handshake appends one byte, and the EOP handshake publishes and clears the completed packet.

What to cover

Requirements

  1. Sample a byte only on a rising edge where valid && ready is true; while valid&&!ready, require valid, sop, eop, and data to stay stable and accept nothing.
  2. Start a new item only on an accepted beat with sop=1, append every accepted byte, and publish on the accepted beat with eop=1.
  3. An accepted byte before SOP, or a second SOP before EOP, reports uvm_error, discards the partial item and offending beat, and returns to IDLE; the offending beat is not reused.
  4. When rst_n is 0, discard any partial item and publish nothing.
Continue practicing
SystemVerilog & UVMConstrain a balanced six-request descriptor set