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DescriptionQ731
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Q731DesignGoogleASIC interview problem

Scale CMOS dynamic power

TechniquesDesignLow powerDynamic powerVoltage scaling
DifficultyEasy
TopicLow Power Design
LanguageSystemVerilog
Format4 choices
01

Problem

For the same block and capacitance, activity factor doubles, supply voltage falls from 1.0 V to 0.9 V, and frequency is unchanged. Using Pdynamic proportional to activity*C*V^2*f, what is the new dynamic-power ratio?

02

Answer choices (4)