Skip to question
asic.fyi

Hardware interview practice

Scale CMOS dynamic power

EasyLow Power DesignSystemVerilog

For the same block and capacitance, activity factor doubles, supply voltage falls from 1.0 V to 0.9 V, and frequency is unchanged. Using Pdynamic proportional to activity*C*V^2*f, what is the new dynamic-power ratio?

Choose one

Answer choices

  1. A. 2.00, because voltage has no effect when clock frequency is unchanged.
  2. B. 1.62, because 2 * 0.9^2 = 1.62.
  3. C. 1.80, because dynamic power scales linearly with voltage rather than voltage squared.
  4. D. 0.81, because only the voltage change affects dynamic power.
Continue practicing
Low Power DesignPower-state transition controllerLow Power DesignControl entry to and exit from memory self-refreshLow Power DesignThrottle with temperature hysteresis