1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ496

Page ↗

Q496DesignDVQualcommASIC interview problem

Check framed serial even parity

TechniquesDVDesignSVAFSM

DifficultyMedium

TopicRTL Design

LanguageSystemVerilog

Requirements4 checkpoints

Problem

Valid cycles carry frame data bits followed by one parity bit. last is asserted only on that parity bit. Implement a serial even-parity checker with a one-cycle result pulse.

Starting declarationSystemVerilog

clk, reset_n
valid, bit_in, last
parity_valid, parity_ok
active-low synchronous reset

Example input and output

Use this case to check your interpretation

Input

Case 1: Data 1,0,1 then parity 0
Case 2: Data 1,0,0 then parity 1
Case 3: last=1 on the first accepted bit

Output

Case 1: Gives parity_valid=1 and parity_ok=1.
Case 2: Gives parity_ok=1.
Case 3: Produces parity_valid=1 and parity_ok=0.

Explanation

The shown result follows by applying this rule: The last bit is compared with, not folded into, the prior-data parity. The cases also demonstrate this requirement: If valid && last is accepted before any data bit, pulse parity_valid for one cycle with parity_ok = 0, clear the accumulator, and begin the next frame cleanly; invalid cycles otherwise hold state.

Requirements (4)

XOR only accepted data bits into an accumulator; treat the accepted last bit as parity, not data.
On an accepted last bit, pulse parity_valid for one cycle and set parity_ok when bit_in equals the accumulated XOR.
Clear the accumulator after every completed frame and during reset.
If valid && last is accepted before any data bit, pulse parity_valid for one cycle with parity_ok = 0, clear the accumulator, and begin the next frame cleanly; invalid cycles otherwise hold state.