1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ475

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Q475DesignAMDASIC interview problem

Calculate setup and hold slack with clock latency

TechniquesDesignSTAClockingRegisters

DifficultyMedium

TopicTiming

LanguageSystemVerilog

Requirements4 checkpoints

Problem

One same-cycle register path uses the numbers below. Positive latency means an edge arrives that many picoseconds after the ideal clock origin. Verify setup and hold arrival and required times; use setup slack as required minus arrival and hold slack as arrival minus required.

Starting declarationSystemVerilog

period=1000 ps; launch latency=50 ps; capture latency=80 ps
setup: Tcq_max=80,Dmax=700,Tsetup=100,Usetup=20 ps
hold: Tcq_min=60,Dmin=40,Thold=80,Uhold=10 ps
report all arrival, required, and slack values in ps

Example input and output

Use this case to check your interpretation

Input

Case 1: Setup arrival is 830 ps and setup required is 960 ps
Case 2: Hold arrival is 150 ps and hold required is 170 ps
Case 3: Add 20 ps to the minimum data delay

Output

Case 1: setup slack is +130 ps
Case 2: hold slack is -20 ps
Case 3: hold arrival becomes 170 ps and hold slack becomes 0 ps

Explanation

The shown result follows by applying this rule: Put launch latency on data arrival and capture latency on the required edge for both checks. The cases also demonstrate this requirement: Identify the exact minimum added data delay needed to make the hold check zero slack while leaving the supplied setup maximum unchanged.

Requirements (4)

For setup, use arrival=Llaunch+Tcq_max+Dmax and required=period+Lcapture-Tsetup-Usetup.
For hold, use arrival=Llaunch+Tcq_min+Dmin and required=Lcapture+Thold+Uhold.
Use setup_slack=setup_required-setup_arrival and hold_slack=hold_arrival-hold_required; report positive slack as pass and negative slack as fail for both checks.
Identify the exact minimum added data delay needed to make the hold check zero slack while leaving the supplied setup maximum unchanged.