1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ955

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Q955ArchDesignAMDASIC interview problem

Write an eight-bit binary-to-Gray converter

TechniquesDesignGray codeFIFO

DifficultyEasy

TopicMemory Systems

LanguageSystemVerilog

Requirements4 checkpoints

Problem

An asynchronous-FIFO pointer helper needs reflected Gray code with zero latency. Write the combinational converter.

Module declarationSystemVerilog

module bin_to_gray8(
  input logic [7:0] bin, output logic [7:0] gray
);

Example input and output

Use this case to check your interpretation

Input

Case 1: bin=8'h00
Case 2: bin=8'h0B
Case 3: bin=8'hFF

Output

Case 1: Produces gray=8'h00.
Case 2: Produces gray=8'h0E.
Case 3: Produces gray=8'h80.

Explanation

The shown result follows by applying this rule: A single XOR of the input with its one-bit logical right shift implements the converter. The cases also demonstrate this requirement: For consecutive two-state binary counts, the two Gray outputs must differ in exactly one bit, including 8'hFF to 8'h00 wraparound.

Requirements (4)

Implement reflected Gray conversion as gray = bin ^ (bin >> 1).
Use purely combinational logic with no clock, reset, latch, or retained state.
Preserve all eight bits, including the most-significant bit and leading zeros.
For consecutive two-state binary counts, the two Gray outputs must differ in exactly one bit, including 8'hFF to 8'h00 wraparound.