DescriptionQ775
Q775DVASIC interview problem
Print a periodic heartbeat
TechniquesClockingDiagnosticsUVM
DifficultyEasy
TopicTemporal Checks
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
Print a still-alive message every period_cycles while simulation runs.
Example input and output
Use this case to check your interpretationInput
period_cycles=3; clock advances through cycle9Output
still-alive messages at cycles3,6,9 with their simulation timestampsExplanation
The forever loop counts three positive edges per report rather than using wall-clock delay.
02
Requirements (4)
- Require period_cycles to be positive.
- Count clock cycles rather than wall-clock time.
- Repeat forever.
- Include simulation time in the message.