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Hardware interview practice

Print a periodic heartbeat

EasyTemporal ChecksSystemVerilog

Print a still-alive message every period_cycles while simulation runs.

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Reviewed example

Work through one case

Input
period_cycles=3; clock advances through cycle9
Expected output
still-alive messages at cycles3,6,9 with their simulation timestamps

The forever loop counts three positive edges per report rather than using wall-clock delay.

What to cover

Requirements

  1. Require period_cycles to be positive.
  2. Count clock cycles rather than wall-clock time.
  3. Repeat forever.
  4. Include simulation time in the message.
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