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DescriptionQ495
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Q495DVASIC interview problem

P_sequencer type coupling

TechniquesUVMVirtual sequence coordination
DifficultyMedium
TopicUVM Components
LanguageSystemVerilog
Format4 choices
01

Problem

A virtual sequence declares p_sequencer as sys_vseqr, but a test accidentally starts it on a bus_sequencer. What is the expected failure mode?

Class declarationSystemVerilog
class sys_vseq extends uvm_sequence;
  `uvm_declare_p_sequencer(sys_vseqr)
  // body uses p_sequencer.bus_sqr
endclass
02

Answer choices (4)