DescriptionQ631
Q631DVASIC interview problem
Config_db build-time precedence
TechniquesUVMConfiguration scoping and precedence
DifficultyMedium
TopicUVM Components
LanguageSystemVerilog
Format4 choices
01
Problem
During build, the test sets mode=1 for env.*. Later, in agent a0's build_phase, a0 sets mode=2 for itself and then gets mode. Both settings match. Under mainstream UVM build-time precedence, which value wins?
Starting declarationSystemVerilog
// In test::build_phase
uvm_config_db#(int)::set(this, "env.*", "mode", 1);
// Later, in a0::build_phase
uvm_config_db#(int)::set(this, "", "mode", 2);
void'(uvm_config_db#(int)::get(this, "", "mode", mode));02