1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

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DescriptionQ048

Q048DVDesignASIC interview problem

Type parameters

TechniquesSystemVerilogElaboration and reuse

DifficultyEasy

TopicSV

LanguageSystemVerilog

Format4 choices

What is the type of port a in this instance?

Module declarationSystemVerilog

module holder #(parameter type T = int) (input T a); endmodule
holder #(.T(logic [7:0])) u (.a(sig));