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Hardware interview practice

Type parameters

EasySystemVerilogSystemVerilog

What is the type of port a in this instance?

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Question code

module holder #(parameter type T = int) (input T a); endmodule
holder #(.T(logic [7:0])) u (.a(sig));
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Answer choices

  1. A. A 32-bit 2-state int
  2. B. An 8-bit 4-state packed logic vector
  3. C. An unpacked array of eight logic elements
  4. D. A dynamically typed port
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