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DescriptionQ244
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Q244DVASIC interview problem

SystemVerilog Assertions (SVA) implication

TechniquesSystemVerilogAssertion timing
DifficultyEasy
TopicTemporal Checks
LanguageSystemVerilog
Format4 choices
01

Problem

For the one-cycle antecedent a, which property is cycle-equivalent to the property shown?

Starting declarationSystemVerilog
assert property (@(posedge clk) a |=> b);
02

Answer choices (4)