1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

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DescriptionQ791

Q791DVDesignASIC interview problem

4-state equality

TechniquesSystemVerilogTypes and resolution

DifficultyEasy

TopicSV

LanguageSystemVerilog

Format4 choices

What does the display print?

Starting declarationSystemVerilog

logic [1:0] a = 2'bx1;
logic [1:0] b = 2'bx1;
initial $display("%0b %0b", a == b, a === b);