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SystemVerilog Logical Equality vs. Case Equality

EasySystemVerilogMultiple choice

What does the display print?

Question code
logic [1:0] a = 2'bx1;
logic [1:0] b = 2'bx1;
initial $display("%0b %0b", a == b, a === b);

Answer choices

  1. A. 1 1
  2. B. 0 1
  3. C. x 1
  4. D. x x

Concise answer

The answer and the key reason

Choose C: the output is x 1. Ordinary equality cannot decide whether vectors containing unknown bits match, so it produces X. Case equality compares X and Z as actual four-state symbols; since both vectors are x1, that comparison produces 1.

Deeper explanation

Work through the implementation and tradeoffs

The == operator performs four-state logical equality. Known mismatches can force a definite false result, but here both high bits are X and no known bit disproves equality. Because the outcome depends on what those unknown bits eventually represent, the first expression remains unknown and %0b displays x.

The === operator is intended for exact four-state comparison. It does not propagate uncertainty from X or Z; instead, those symbols must occupy matching positions just like 0 and 1. Both operands have X in bit 1 and 1 in bit 0, so the second expression is true. Use this distinction carefully in checkers.

What to remember

  • Logical equality can return X
  • Case equality compares X/Z literally
  • The result is x 1

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