1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ096

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Q096DesignGoogleASIC interview problem

Release reset synchronously

TechniquesDesignRDCResetRecovery/removal

DifficultyEasy

TopicReset Domain Crossing

LanguageSystemVerilog

Requirements4 checkpoints

Problem

A destination clock domain needs an active-low reset that asserts immediately but deasserts only on a destination-clock edge after two clean samples. Write the two-flop reset synchronizer RTL.

Starting declarationSystemVerilog

input logic dst_clk;
input logic arst_n;
output logic srst_n;

Example input and output

Use this case to check your interpretation

Input

arst_n rises before destination edges E1 and E2

Output

srst_n=0 after E1 and srst_n=1 after E2

Explanation

Each edge advances one clean sample. If arst_n falls at any time, both stages clear immediately and release restarts.

Requirements (4)

When arst_n falls, asynchronously drive both synchronizer stages and srst_n to 0 without waiting for dst_clk.
When arst_n rises, shift a 1 through two destination-clocked stages using nonblocking assignments.
Drive srst_n only from the second stage, so it rises on the second dst_clk edge after arst_n is high.
Do not add combinational gating on srst_n; if arst_n falls during release, assertion again takes effect immediately.