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DescriptionQ677
Q677DVDesignQualcommASIC interview problem

Identify an asynchronous-reset recovery violation

TechniquesDVDesignSVAResetSTA
DifficultyMedium
TopicClock and Reset Domains
LanguageSystemVerilog
Format4 choices
01

Problem

A flip-flop library requires 80 ps recovery. Asynchronous reset deasserts 30 ps before the next active clock edge. Which conclusion is correct?

02

Answer choices (4)