DescriptionQ953
Q953DVASIC interview problem
Check burst length and the accepted last beat
TechniquesBurst protocolBackpressureWLASTQueue
DifficultyHard
TopicTemporal Checks
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
Commands announce burst lengths from 1 to 16 and may queue. Count only accepted data beats and require WLAST exactly on each command's final beat.
Starting declarationSystemVerilog
input logic clk, rst_n, cmd_valid, cmd_ready;
input logic [4:0] cmd_len;
input logic wvalid, wready, wlast;Example input and output
Use this case to check your interpretationInput
cmd_len = 3; accepted data beats carry WLAST = 0, 0, 1Output
pass and retire one commandExplanation
Only the three WVALID && WREADY events count, and WLAST is asserted on exactly the third accepted beat.
02
Requirements (4)
- Queue cmd_len only on cmd_valid && cmd_ready.
- Count a data beat only on wvalid && wready.
- Compare WLAST with the final accepted beat of the queue-front command.
- Report invalid length, data without a command, early or missing WLAST, and end-of-test leftovers.