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Hardware interview practice

Check burst length and the accepted last beat

HardTemporal ChecksSystemVerilog

Commands announce burst lengths from 1 to 16 and may queue. Count only accepted data beats and require WLAST exactly on each command's final beat.

Starting point

Question code

input logic clk, rst_n, cmd_valid, cmd_ready;
input logic [4:0] cmd_len;
input logic wvalid, wready, wlast;
Reviewed example

Work through one case

Input
cmd_len = 3; accepted data beats carry WLAST = 0, 0, 1
Expected output
pass and retire one command

Only the three WVALID && WREADY events count, and WLAST is asserted on exactly the third accepted beat.

What to cover

Requirements

  1. Queue cmd_len only on cmd_valid && cmd_ready.
  2. Count a data beat only on wvalid && wready.
  3. Compare WLAST with the final accepted beat of the queue-front command.
  4. Report invalid length, data without a command, early or missing WLAST, and end-of-test leftovers.