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DescriptionQ926
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Q926DesignArchMetaASIC interview problem

Clocked assignment for a register chain

TechniquesDesignSystemVerilogalways_ffPipeline
DifficultyEasy
TopicRTL Design
LanguageSystemVerilog
Format4 choices
01

Problem

Two registers form a pipeline: q1 captures d and q2 captures the previous value of q1 on each rising edge. Which implementation gives the intended register-to-register behavior?

02

Answer choices (4)