Hardware interview practice
Clocked assignment for a register chain
Two registers form a pipeline: q1 captures d and q2 captures the previous value of q1 on each rising edge. Which implementation gives the intended register-to-register behavior?
Choose one
Answer choices
- A. Use blocking assignments to q1 and then q2 in one rising-edge process.
- B. Drive q1 with a continuous assignment and assign q2 in an always_comb block.
- C. Use nonblocking assignments to q1 and q2 in one always_ff block triggered by the rising clock edge.
- D. Assign q1 from two separate always_ff blocks and let the simulator resolve the latest value.