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DescriptionQ899
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Q899DVASIC interview problem

UVM global heartbeat component

TechniquesUVMWatchdogProgress counter
DifficultyMedium
TopicTemporal Checks
LanguageSystemVerilog
Requirements4 checkpoints
01

Problem

Design a configurable Universal Verification Methodology (UVM) component that receives progress notifications and ends the simulation when no activity occurs within a time window.

Example input and output

Use this case to check your interpretation
Input
heartbeat_window=100us; trigger() at t=60us and t=140us; no later trigger
Output
trigger_count=2, last_activity_time=140us; inactivity fatal at t=240us
Explanation

Each trigger restarts the window. A trigger visible by the nonblocking-assignment region at exactly t=240us would still prevent the timeout.

02

Requirements (4)

  • Expose an enable knob and heartbeat window through uvm_config_db.
  • Record last activity time and trigger count for diagnostics.
  • Race the next activity against the timeout and cancel the losing process.
  • Count a trigger visible by the nonblocking-assignment region at the exact deadline as on time.