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Hardware interview practice

UVM global heartbeat component

MediumTemporal ChecksSystemVerilog

Design a configurable Universal Verification Methodology (UVM) component that receives progress notifications and ends the simulation when no activity occurs within a time window.

Reviewed example

Work through one case

Input
heartbeat_window=100us; trigger() at t=60us and t=140us; no later trigger
Expected output
trigger_count=2, last_activity_time=140us; inactivity fatal at t=240us

Each trigger restarts the window. A trigger visible by the nonblocking-assignment region at exactly t=240us would still prevent the timeout.

What to cover

Requirements

  1. Expose an enable knob and heartbeat window through uvm_config_db.
  2. Record last activity time and trigger count for diagnostics.
  3. Race the next activity against the timeout and cancel the losing process.
  4. Count a trigger visible by the nonblocking-assignment region at the exact deadline as on time.