1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ896

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Q896DesignArchNVIDIAASIC interview problem

Find the lowest set lane

TechniquesRTL DesignRTL / Microarchitecturefind the lowest set lane

DifficultyEasy

TopicRTL Design

LanguageSystemVerilog

Requirements4 checkpoints

Problem

An eight-lane issue block must select the lowest-numbered requested lane. Write a combinational SystemVerilog find-first-set block and a self-checking test loop.

Starting declarationSystemVerilog

input logic [7:0] req;
output logic valid;
output logic [2:0] index;

Example input and output

Use this case to check your interpretation

Input

req=8'b0000_0000.

Output

valid=0 and index=0.

Explanation

No lane is requested, so the specified empty-case defaults remain selected.

Requirements (4)

If req is nonzero, set valid=1 and index to the smallest i for which req[i]=1.
If req is zero, set valid=0 and index=0.
Use combinational synthesizable RTL and make the priority explicit.
The test code must iterate all 256 request values and compare against an independent loop model.