DescriptionQ893
Q893DesignArchASIC interview problem
Detect duplicate valid cache tags
TechniquesAssociative comparePriority encoderValid bits
DifficultyMedium
TopicRTL Datapaths
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
Design a checker for a small fully associative cache set that reports whether any two valid ways contain the same tag and returns the earliest matching way pair.
Example input and output
Use this case to check your interpretationInput
valid=4'b1111; tags by way=[A,B,A,A]Output
duplicate=1; way_a=0; way_b=2Explanation
Way pairs (0,2) and (0,3) match, and the nested lowest-way priority chooses (0,2); invalid ways would not participate.
02
Requirements (4)
- Compare only distinct valid ways and return way_a < way_b.
- Ignore equal tags in invalid ways.
- Use lowest-way lexicographic priority when several duplicate pairs exist.
- Accept check only when check_ready is high, pulse done once per accepted check, and return zero indices when no duplicate exists.