DescriptionQ889
Q889DesignNVIDIAASIC interview problem
Track parity history with two state bits
TechniquesDesignSystemVerilogParityState minimization
DifficultyMedium
TopicRTL Design
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
For valid symbols X, Y, W, and Z, assert flag whenever the number of X symbols since reset is even and the number of W symbols is odd.
Starting declarationSystemVerilog
// X=2'b00, Y=2'b01, W=2'b10, Z=2'b11
input logic clk, rst_n, valid;
input logic [1:0] symbol;
output logic flag;Example input and output
Use this case to check your interpretationInput
After reset, valid symbols X, X, W, Y, ZOutput
flag=1 after W and remains 1 through Y and ZExplanation
Two X symbols give even X parity, and one W gives odd W parity.
02
Requirements (4)
- Store only X parity and W parity.
- Toggle each parity only for its valid matching symbol.
- Ignore Y, Z, and invalid cycles.
- Define flag from the registered history after each accepted edge.