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Hardware interview practice

Track parity history with two state bits

MediumRTL DesignSystemVerilog

For valid symbols X, Y, W, and Z, assert flag whenever the number of X symbols since reset is even and the number of W symbols is odd.

Starting point

Question code

// X=2'b00, Y=2'b01, W=2'b10, Z=2'b11
input logic clk, rst_n, valid;
input logic [1:0] symbol;
output logic flag;
Reviewed example

Work through one case

Input
After reset, valid symbols X, X, W, Y, Z
Expected output
flag=1 after W and remains 1 through Y and Z

Two X symbols give even X parity, and one W gives odd W parity.

What to cover

Requirements

  1. Store only X parity and W parity.
  2. Toggle each parity only for its valid matching symbol.
  3. Ignore Y, Z, and invalid cycles.
  4. Define flag from the registered history after each accepted edge.