DescriptionQ881
Q881DVASIC interview problem
Verify sorted signed squares
TechniquesDVSigned arithmeticTwo pointersSortingBounds
DifficultyEasy
TopicReference Models
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
Verify a block that accepts up to 16 sorted signed 16-bit samples and returns every square in nondecreasing order without losing duplicates.
Starting declarationSystemVerilog
logic clk, rst_n, start;
logic [4:0] count;
logic signed [15:0] sample [16];
logic busy, done, request_error;
logic [30:0] square [16];
parameter int MAX_LATENCY = 20;Example input and output
Use this case to check your interpretationInput
count=5; sorted signed samples=[-4,-1,0,3,10]Output
active output=[0,1,9,16,100]; every inactive lane=0Explanation
Widened squaring plus an independent sort preserves every active value, retains duplicates, and zeroes every inactive output lane.
02
Requirements (4)
- Accept counts 0 through 16 only when active samples are already nondecreasing.
- Widen every signed input before multiplication so -32768 squares exactly.
- Compare all active outputs, duplicate multiplicities, sorted order, and zero unused lanes.
- Invalid requests return request_error with all lanes zero; completion is bounded and reset-cancelable.