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Hardware interview practice

Verify sorted signed squares

EasyReference ModelsSystemVerilog

Verify a block that accepts up to 16 sorted signed 16-bit samples and returns every square in nondecreasing order without losing duplicates.

Starting point

Question code

logic clk, rst_n, start;
logic [4:0] count;
logic signed [15:0] sample [16];
logic busy, done, request_error;
logic [30:0] square [16];
parameter int MAX_LATENCY = 20;
Reviewed example

Work through one case

Input
count=5; sorted signed samples=[-4,-1,0,3,10]
Expected output
active output=[0,1,9,16,100]; every inactive lane=0

Widened squaring plus an independent sort preserves every active value, retains duplicates, and zeroes every inactive output lane.

What to cover

Requirements

  1. Accept counts 0 through 16 only when active samples are already nondecreasing.
  2. Widen every signed input before multiplication so -32768 squares exactly.
  3. Compare all active outputs, duplicate multiplicities, sorted order, and zero unused lanes.
  4. Invalid requests return request_error with all lanes zero; completion is bounded and reset-cancelable.
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