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DescriptionQ088
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Q088DVASIC interview problem

A Single Send Command Produces Two Transfers

TechniquesDVWaveform DebuggingReady/valid
DifficultyEasy
TopicWaveform Debugging
LanguageSystemVerilog
Format4 choices
01

Problem

send_one requests one output beat. The receiver is continuously ready. A transfer occurs at each edge where valid and ready are both 1. Rule to apply: Each one-cycle send_one pulse must produce exactly one transfer. After that transfer, valid must be 0 on the next edge unless a new send_one pulse occurs. Why does the receiver count two transfers?

Waveform for A Single Send Command Produces Two Transfers. Signals: send_one, valid, ready, data. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
02

Answer choices (4)