DescriptionQ833
Q833DesignArchAppleASIC interview problem
Accumulate a four-lane signed dot product
TechniquesRTL DesignRTL / Microarchitectureaccumulate a four-lane signed dot product
DifficultyMedium
TopicRTL Design
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
A small signal-processing block accepts four signed byte pairs and uses one multiplier for a fixed four-cycle calculation. Implement synthesizable SystemVerilog RTL for the fixed-latency dot-product engine.
Starting declarationSystemVerilog
input logic clk, rst_n, start;
input logic signed [7:0] a[4], b[4];
output logic busy, done;
output logic signed [17:0] result;Example input and output
Use this case to check your interpretationInput
At C0, start is accepted with a={1,2,3,4} and b={5,6,7,8}.Output
After C4, done=1 and result=70.Explanation
The engine snapshots the operands and accumulates one lane per cycle: 1×5 + 2×6 + 3×7 + 4×8 = 70, then completes on the fourth MAC edge.
02
Requirements (4)
- Accept start only on a rising edge with busy=0, snapshot all eight inputs, set busy, and ignore every start sampled while busy=1.
- Accumulate one signed lane product per cycle in index order; keep every product and the running sum signed at 18 bits.
- For a start accepted at C0, drive done=1 and the exact sum after edge C4; busy is 1 after C0 through C3, then 0 after C4, and done is otherwise 0.
- When rst_n=0 at a rising edge, clear busy, done, result, the accumulator, and the lane index; the reset edge accepts no start.