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DescriptionQ820
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Q820ArchIntelASIC interview problem

Preserve Correct State in a Five-Stage Pipeline

TechniquesArchClockingPipeline
DifficultyHard
TopicComputer Architecture
LanguageSystemVerilog
Format4 choices
01

Problem

An in-order IF/ID/EX/MEM/WB core has full ALU forwarding, detects a load-use hazard in ID, resolves branches in EX, and can see a data-access fault in MEM. Architectural exceptions must be precise. Which control policy is correct?

02

Answer choices (4)