Skip to question
asic.fyi
DesignVerificationSystemVerilogFirmwareArchitectureInterviews
asic.fyi/Interview questions/Preserve Correct State in a Five-Stage Pipeline

Hardware interview practice

Preserve Correct State in a Five-Stage Pipeline

HardComputer ArchitectureSystemVerilog

An in-order IF/ID/EX/MEM/WB core has full ALU forwarding, detects a load-use hazard in ID, resolves branches in EX, and can see a data-access fault in MEM. Architectural exceptions must be precise. Which control policy is correct?

Try it in the question bankReason first. Then compare.

Keep this exact question selected while you check your answer and review the full solution.

Practice this question →
Choose one

Answer choices

  1. A. Forward the load address as load data to avoid the stall, never flush on a taken branch, and repair any wrong-path writes after WB.
  2. B. Handle every dependency by flushing the complete pipeline and restarting at the consumer instruction; branch and exception age do not affect which writes are allowed.
  3. C. Stall the dependent instruction for a load-use gap, forward other available results, flush younger instructions when an EX branch is taken, and on a MEM fault allow older instructions to complete while suppressing the faulting instruction's writeback and flushing all younger state before entering the handler.
  4. D. On a MEM fault, immediately discard every older and younger instruction, including one already committed in WB, so the machine restarts from an empty pipeline.
asic.fyi · Learn silicon end to end.info@asic.fyi