DescriptionQ080
Q080ArchAppleASIC interview problem
Match hit-under-miss responses by transaction ID
TechniquesArchMicroarchitectureInterconnectMatchHit-Under-Miss
DifficultyMedium
TopicComputer Architecture
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
A cache may hold one miss while later hits return first. A scoreboard therefore cannot compare responses only in request order. Implement a SystemVerilog reference scoreboard keyed by four-bit transaction ID.
Class declarationSystemVerilog
class hum_scoreboard;
function void request(bit [3:0] id, bit hit, bit [31:0] hit_data);
function void fill(bit [3:0] miss_id, bit [31:0] fill_data);
function void response(bit [3:0] id, bit [31:0] data);
function int unsigned errors();Example input and output
Use this case to check your interpretationInput
request(1, miss), request(2, hit, 0x22), response(2, 0x22), fill(1, 0x11), response(1, 0x11).Output
errors() returns 0 and both IDs retire.Explanation
The hit may respond before the miss, while the fill supplies ID 1's expected data before its matching response arrives.
02
Requirements (4)
- An ID must not be reused while outstanding. A hit records hit_data immediately; a miss records no data and is legal only when no other miss is outstanding.
- fill is legal only for the current miss ID, supplies that ID's expected data, and clears the one-miss resource without completing the response obligation.
- response may arrive in any ID order but is legal only after that ID has expected data; compare data with case equality, count one error on mismatch, and then retire the ID.
- Construction starts empty with errors=0. Duplicate IDs, a second concurrent miss, wrong or duplicate fill, early response, and response for an unknown ID each increment errors once without corrupting other entries.