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DescriptionQ792
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Q792DVDesignQualcommASIC interview problem

Recognize and repair a combinational loop

TechniquesDesignRTL
DifficultyEasy
TopicSV
LanguageSystemVerilog
Format4 choices
01

Problem

RTL contains `assign a = ~b; assign b = a;` with no storage element or intentional oscillator primitive. What is the correct engineering response?

02

Answer choices (4)