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Hardware interview practice

Recognize and repair a combinational loop

EasySystemVerilogSystemVerilog

RTL contains `assign a = ~b; assign b = a;` with no storage element or intentional oscillator primitive. What is the correct engineering response?

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Answer choices

  1. A. Keep the loop and add a false-path constraint; a timing exception makes its functional value deterministic.
  2. B. Add a second continuous assignment driver to a; multiple drivers guarantee that the loop settles.
  3. C. Synthesis always resolves the equations to a stable Boolean constant, so no review is needed.
  4. D. Treat it as an unintended combinational loop that can fail to converge or oscillate; correct the equations or insert architecturally intended registered state.
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