DescriptionQ766
Q766DesignNVIDIAASIC interview problem
Implement a parameterized shift register
TechniquesDesignSystemVerilogShift registerParameters
DifficultyEasy
TopicRTL Design
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
Write a parameterized serial-in, parallel-out register that shifts toward the MSB on enabled clock edges and supports every width W >= 2.
Starting declarationSystemVerilog
parameter int W = 8;
input logic clk, rst_n, en, serial_in;
output logic [W-1:0] q;Example input and output
Use this case to check your interpretationInput
W=8, q=8'b0000_0101, serial_in=1, en=1; then a rising edgeOutput
q=8'b0000_1011Explanation
The old low seven bits shift up and the new serial bit enters bit 0.
02
Requirements (4)
- Use active-low asynchronous reset to zero.
- Shift only when en is high.
- Load serial_in into bit 0 and move existing bits toward the MSB.
- Hold state when disabled and require W >= 2.