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Hardware interview practice

Implement a parameterized shift register

EasyRTL DesignSystemVerilog

Write a parameterized serial-in, parallel-out register that shifts toward the MSB on enabled clock edges and supports every width W >= 2.

Starting point

Question code

parameter int W = 8;
input  logic clk, rst_n, en, serial_in;
output logic [W-1:0] q;
Reviewed example

Work through one case

Input
W=8, q=8'b0000_0101, serial_in=1, en=1; then a rising edge
Expected output
q=8'b0000_1011

The old low seven bits shift up and the new serial bit enters bit 0.

What to cover

Requirements

  1. Use active-low asynchronous reset to zero.
  2. Shift only when en is high.
  3. Load serial_in into bit 0 and move existing bits toward the MSB.
  4. Hold state when disabled and require W >= 2.