1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ742

Q742DesignArchASIC interview problem

Compact valid cache-line words in place

TechniquesStable compactionValid bitsBounded array

DifficultyMedium

TopicRTL Datapaths

LanguageSystemVerilog

Requirements4 checkpoints

Compact the valid words in a bounded cache-line register bank toward slot zero while preserving order. Clear every vacated valid bit and data slot.

Use this case to check your interpretation

Input

valid=5'b10110; data=[dirty,A,B,dirty,C] by slot 0..4

Output

valid=5'b00111; data=[A,B,C,0,0]

Explanation

Compaction reads only original valid slots in order and clears both data and validity in every vacated suffix slot.

Use the valid bitmap, not the data value, to decide which words to retain.
Preserve the original order of all valid entries.
Replace the internal line state with the compacted result without overwriting unread values.
Provide fixed busy/done behavior and support all-valid and all-invalid lines.