DescriptionQ725
Q725DVMicronASIC interview problem
Scoreboard bank state and tagged DDR reads
TechniquesDVSystemVerilogUVMScoreboardreads
DifficultyHard
TopicSystemVerilog & UVM
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
A command monitor reports ACT, PRE, WR, and RD operations, while a response monitor reports tagged read data in any order. Implement the SystemVerilog scoreboard state model and response matching.
Class declarationSystemVerilog
class ddr_scoreboard; // cmd: ACT=0, PRE=1, WR=2, RD=3
function void command(bit [1:0] cmd, bit [2:0] bank, bit [15:0] row, bit [9:0] col, bit [5:0] id, bit [31:0] data);
function void response(bit [5:0] id, bit [31:0] data);
function int unsigned errors();
endclassExample input and output
Use this case to check your interpretationInput
Commands ACT(bank1,row7), WR(bank1,col2,0xAA), RD(bank1,col2,id3), followed by response(id3,0xAA).Output
errors() returns 0 and ID 3 is no longer outstanding.Explanation
The open row forms the sparse-memory key, the read records 0xAA by ID, and the matching response retires that expectation.
02
Requirements (4)
- Only bank values 0 through 3 are legal. For a legal bank, ACT opens it at row only if closed and PRE closes only an open bank; an illegal bank or state command increments errors once and changes no state.
- WR and RD are legal only for an open bank and use that bank's open row; WR updates a sparse model at (bank,row,col). Unwritten locations read as 32'h0000_0000.
- A legal RD requires an ID not already outstanding and records expected data by ID; responses may reorder, compare by case equality, and retire the matching ID even on mismatch.
- Illegal bank numbers, duplicate IDs, unknown responses, and RD/WR while closed each increment errors once and leave all unrelated state unchanged; construction starts closed and empty with errors=0.