1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ604

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Q604DVGoogleASIC interview problem

Build a FIFO UVM testbench

TechniquesDVUVMFIFOScoreboardCoverage

DifficultyMedium

TopicUVM

LanguageSystemVerilog

Requirements4 checkpoints

Problem

A depth-8 non-fall-through synchronous FIFO must be verified for ordering, flags, simultaneous operations, overflow attempts, and underflow attempts. Design the minimum reusable UVM environment and concrete checking rules.

Starting declarationSystemVerilog

clk, rst_n
wr_valid, wr_ready, wr_data[15:0]
rd_valid, rd_ready, rd_data[15:0]
full, empty

Example input and output

Use this case to check your interpretation

Input

Model contains [A,B]; rd_valid=rd_ready=wr_valid=wr_ready=1 with wr_data=C

Output

Compare rd_data with A, then model becomes [B,C]

Explanation

Processing the read against pre-edge state before appending the write preserves simultaneous-transfer semantics and occupancy.

Requirements (4)

Use an active agent to drive writes and read-ready, a monitor to publish accepted writes and reads, and a scoreboard with a reference queue.
Use a non-fall-through contract: before each nonreset edge, empty==(model_size==0), full==(model_size==8), rd_valid==!empty, and wr_ready==!full; accept transfers only from those sampled handshakes.
On an edge with rst_n=0, ignore handshakes and clear the model; require empty=1 and full=0 on the following cycle. On a simultaneous accepted read/write, compare and remove the pre-edge head before appending the write.
Cover occupancies 0 through 8, full/empty transitions, simultaneous accepted read/write, blocked write at full, and blocked read at empty.